LM3S6100 Datasheet, PDF (11/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 7-7.
Revision History .................................................................................................. 20
Documentation Conventions ................................................................................ 26
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 46
Processor Register Map ....................................................................................... 47
PSR Register Combinations ................................................................................. 52
Memory Map ....................................................................................................... 60
Memory Access Behavior ..................................................................................... 62
SRAM Memory Bit-Banding Regions .................................................................... 64
Peripheral Memory Bit-Banding Regions ............................................................... 64
Exception Types .................................................................................................. 70
Interrupts ............................................................................................................ 71
Exception Return Behavior ................................................................................... 75
Faults ................................................................................................................. 76
Fault Status and Fault Address Registers .............................................................. 77
Cortex-M3 Instruction Summary ........................................................................... 79
Core Peripheral Register Regions ......................................................................... 83
Memory Attributes Summary ................................................................................ 86
TEX, S, C, and B Bit Field Encoding ..................................................................... 89
Cache Policy for Memory Attribute Encoding ......................................................... 90
AP Bit Field Encoding .......................................................................................... 90
Memory Region Attributes for Stellaris Microcontrollers .......................................... 90
Peripherals Register Map ..................................................................................... 91
Interrupt Priority Levels ...................................................................................... 116
Example SIZE Field Values ................................................................................ 144
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 148
JTAG_SWD_SWO Signals (108BGA) ................................................................. 149
JTAG Port Pins Reset State ............................................................................... 149
JTAG Instruction Register Commands ................................................................. 156
System Control & Clocks Signals (100LQFP) ...................................................... 160
System Control & Clocks Signals (108BGA) ........................................................ 160
Reset Sources ................................................................................................... 161
Clock Source Options ........................................................................................ 167
Possible System Clock Frequencies Using the SYSDIV Field ............................... 169
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 169
System Control Register Map ............................................................................. 172
RCC2 Fields that Override RCC fields ................................................................. 186
Flash Protection Policy Combinations ................................................................. 217
User-Programmable Flash Memory Resident Registers ....................................... 220
Flash Register Map ............................................................................................ 220
GPIO Pins With Non-Zero Reset Values .............................................................. 243
GPIO Pins and Alternate Functions (100LQFP) ................................................... 243
GPIO Pins and Alternate Functions (108BGA) ..................................................... 243
GPIO Signals (100LQFP) ................................................................................... 244
GPIO Signals (108BGA) ..................................................................................... 245
GPIO Pad Configuration Examples ..................................................................... 250
GPIO Interrupt Configuration Example ................................................................ 250
June 18, 2012
11
Texas Instruments-Production Data