LM3S6100 Datasheet, PDF (439/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge
(MACRIS/MACIACK), offset 0x000
The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this
register gives the current status value of the corresponding interrupt prior to masking. On a write,
setting any bit clears the corresponding interrupt status bit.
Reads
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
PHYINT MDINT RXER
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
19
18
17
16
RO
0
3
FOV
RO
0
RO
RO
0
0
2
TXEMP
RO
0
1
TXER
RO
0
RO
0
0
RXINT
RO
0
Bit/Field
31:7
6
5
4
Name
reserved
PHYINT
MDINT
RXER
Type
RO
RO
RO
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occurred. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
0
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
0
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
3
FOV
RO
0
FIFO Overrun
When set, indicates that an overrun was encountered on the receive
FIFO.
June 18, 2012
439
Texas Instruments-Production Data