LM3S6100 Datasheet, PDF (16/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Table of Contents
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 200
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 201
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 203
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 205
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 207
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 209
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 211
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 213
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 214
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 215
Internal Memory ........................................................................................................................... 216
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 222
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 223
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 224
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 226
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 227
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 228
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 230
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 231
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 232
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 233
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 234
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 235
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 236
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 237
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 238
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 239
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 240
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 241
General-Purpose Input/Outputs (GPIOs) ................................................................................... 242
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 253
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 254
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 255
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 256
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 257
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 258
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 259
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 260
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 261
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 262
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 264
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 265
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 266
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 267
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 268
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 269
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 270
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 271
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June 18, 2012
Texas Instruments-Production Data