LM3S6100 Datasheet, PDF (497/559 Pages) Texas Instruments – Stellaris® LM3S6100 Microcontroller

Stellaris^® LM3S6100 Microcontroller
Table 15-3. Signals by Function, Except for GPIO (continued)
Function
Pin Name Pin Number Pin Type Buffer Type^a
Description
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
JTAG/SWD/SWO
TDI
80
I
TTL
JTAG/SWD CLK.
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I/O
TTL
JTAG TMS and SWDIO.
TRST
89
I
TTL
JTAG TRST.
GND
9
-
Power Ground reference for logic and I/O pins.
15
21
33
39
45
54
57
63
69
82
87
94
GNDA
4
-
Power The ground reference for the analog circuits (
97
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
LDO
Power
7
-
Power Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
VDD
8
-
Power Positive supply for I/O and some logic.
20
32
44
55
56
68
81
93
VDD25
14
-
Power Positive supply for most of the logic function,
38
including the processor core and most peripherals.
62
88
VDDA
3
-
Power The positive supply for the analog circuits (ADC,
98
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in “Recommended DC Operating
Conditions” on page 513, regardless of system
implementation.
June 18, 2012
497
Texas Instruments-Production Data