DS90UR905Q-Q1 Datasheet, PDF (9/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
DS90UR906Q-Q1 Deserializer Pin Functions⁽¹⁾ (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
RFB
18 [B1]
STRAP Pixel clock output strobe edge select — pin or register control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
with pulldown RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
SSC[3:0]
34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP
I, LVCMOS
with pulldown
Spread spectrum clock generation (SSCG) range select — pin or register control
See Table 4 and Table 5.
CONTROL AND CONFIGURATION
BISTEN
44
I, LVCMOS
with pulldown
BIST enable input — optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
ID[x]
56
I, Analog
Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩ pullup to 1.8-V rail (see Table 10).
NC
1, 15, 16,
30, 31, 45,
46, 60
—
Not connected
Leave pin open (float)
PDB
Power-down mode input
PDB = 1, deserializer is enabled (normal operation).
59
I, LVCMOS Refer to Power Up Requirements and PDB Pin.
with pulldown PDB = 0, deserializer is in power down.
When the deserializer is in the power-down state, the LVCMOS output state is determined by
Table 6. Control Registers are RESET.
RES
47
I, LVCMOS
with pulldown
Reserved - tie LOW
SCL
3
I, LVCMOS
Serial control bus clock input — optional
SCL requires an external pullup resistor to V_DDIO.
SDA
2
I/O, LVCMOS Serial control bus data input/output — optional
Open-Drain SDA requires an external pullup resistor to V_DDIO.
FPD-LINK II SERIAL INTERFACE
CMF
Common-mode filter
51
I, Analog VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver
common-mode noise immunity. Recommended value is 0.1 μF or higher.
CMLOUTN
53
O, LVDS
Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable.
CMLOUTP
52
O, LVDS
Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable.
RIN+
49
I, LVDS True input. The input must be AC coupled with a 100-nF capacitor.
RIN-
50
POWER AND GROUND⁽⁵⁾
I, LVDS Inverting input. The input must be AC coupled with a 100-nF capacitor.
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDCMLO
54
Power RX high-speed logic power, 1.8 V ±5%
VDDL
29
Power Logic power, 1.8 V ±5%
VDDIO
VDDIR
13, 24, 38
48
Power
Power
LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10% (V_DDIO)
Input power, 1.8 V ±5%
VDDPR
57
Power PLL power, 1.8 V ±5%
VDDR
43, 55
Power RX high-speed logic power, 1.8 V ±5%
VDDSC
4, 58
Power SSCG power, 1.8 V ±5%
(5) The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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