DS90UR905Q-Q1 Datasheet, PDF (27/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
NOTE
In power down, the optional Serial Bus Control Registers are RESET.
8.3.3.3.2 Serializer Stop Clock Feature
The serializer will enter a low power SLEEP state when the PCLK is stopped. A STOP condition is detected
when the input clock frequency is less than 3 MHz. The clock should be held at a static LOW or HIGH state.
When the PCLK starts again, the Ser will then lock to the valid input PCLK and then transmits the RGB data to
the deserializer.
NOTE
In STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
The serializer parallel bus and serial bus interface can operate with 1.8 V or 3.3 V levels (V_DDIO) for host
compatibility. The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the PCLK. If RFB is Low, input data is latched on the Falling edge of the PCLK. serializer and
deserializer maybe set differently. This feature may be controlled by the external pin or by register.
8.3.3.5 Optional Serial Bus Control
See Optional Serial Bus Control.
8.3.3.6 Optional BIST Mode
See Built-In Self Test (BIST).
8.3.4 Deserializer Functional Description
The deserializer converts a single input serial data stream to a wide parallel output bus, and also provides a
signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins and
strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the link
by supporting: an equalizer input and also the FPD-Link II data coding that provides randomization, scrambling,
and DC balanacing of the data. The deserializer includes multiple features to reduce EMI associated with display
data transmission. This includes the randomization and scrambling of the data and also the output spread
spectrum clock generation (SSCG) support. The deserializer features power saving features with a power-down
mode, and optional LVCMOS (1.8 V) interface compatibility.
8.3.4.1 Signal Quality Enhancers
8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the
deserializer input.
NOTE
This function cannot be seen at the RxIN± input but can be observed at the serial test port
(CMLOUTP/N) enabled through the Serial Bus control registers. The equalization feature
may be controlled by the external pin or by register.
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