DS90UR905Q-Q1 Datasheet, PDF (37/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
8.3.6 Optional Serial Bus Control
The serializer and deserializer may also be configured by the use of a serial control bus that is I²C protocol
compatible. By default, the I²C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write
of 01'h to reg_0x00'h will enable or allow configuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since multiple addresses are supported (see Figure 34).
The serial bus is comprised of three pins. The SCL is a serial bus clock Input. The SDA is the serial bus data
input/output signal. Both SCL and SDA signals require an external pullup resistor to V_DDIO. For most applications
a 4.7-k pullup resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive loading and data
rate requirements. The signals are either pulled High, or driven Low.
1.8V
HOST
SCL
SDA
V_DDIO
4.7k
4.7k
10 k
ID[X]
R_ID
SER
or
SCL _DES
SDA
To other
Devices
Figure 34. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to V_DD (1.8V, NOT V_DDIO) with a 10 kΩ resistor; or a 10-kΩ pullup resistor (to
V_DD1.8V, NOT V_DDIO) and a pulldown resistor of the recommended value to set other three possible addresses
may be used. See Table 10 for the serializer and Table 11 for the deserializer. Do not tie ID[x] directly to VSS.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH (see
Figure 35).
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 35. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.
NOTE
During initial power-up, a delay of 10 ms will be required before the I²C will respond.
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