DS90UR905Q-Q1 Datasheet, PDF (30/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
www.ti.com
8.3.4.3 Power-Saving Features
8.3.4.3.1 Deserializer Power-Down Feature (PDB)
The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the system to save power, disabling the deserializer when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied High and the deserializer will enter power down when the serial
stream stops. When the serial stream starts up again, the deserializer will lock to the input stream and assert the
LOCK pin and output valid data. In power-down mode, the Data and PCLK output states are determined by the
OSS_SEL status.
NOTE
In power down, the optional Serial Bus Control Registers are RESET.
8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
The deserializer will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition
is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer
will then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
8.3.4.4 Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS90UR906Q-Q1 completes its lock sequence
to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and PCLK outputs. The PCLK output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the RGB/VS/HS/DE
outputs are based on the OSS_SEL setting (STRAP PIN configuration or register).
8.3.4.5 Deserializer Oscillator Output (Optional)
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or by register (see Table 7 and Table 8).
Table 6. OSS_SEL and PDB Configuration — Deserializer Outputs⁽¹⁾
SERIAL
INPUT
X
Static
Static
Active
INPUTS
PDB
L
H
H
H
OSS_SEL
X
L
H
X
PCLK
Z
L
Z
Active
OUTPUTS
RGB/HS/VS/DE
LOCK
Z
Z
L
L
Z*
L
Active
H
(1) If pin is strapped HIGH, output will be pulled up
PASS
Z
L
L
H
30
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