DS90UR905Q-Q1 Datasheet, PDF (7/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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NKB Package
60-Pin WQFN
Top View
DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
NC 46
RES 47
VDDIR 48
RIN+ 49
RIN- 50
CMF 51
CMLOUTP 52
CMLOUTN 53
VDDCMLO 54
VDDR 55
ID[x] 56
VDDPR 57
VDDSC 58
PDB 59
NC 60
DS90UR906Q
TOP VIEW
DAP = GND
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
30 NC
29 VDDL
28 G[0]/OSC_SEL[0]
27 G[1]/OSC_SEL[1]
26 G[2]/OSC_SEL[2]
25 G[3]
24 VDDIO
23 G[4]/EQ[0]
22 G[5]/EQ[1]
21 G[6]/EQ[2]
20 G[7]/EQ[3]
19 B[0]
18 B[1]/RFB
17 B[2]/OSS_SEL
16 NC
DS90UR906Q-Q1 Deserializer Pin Functions⁽¹⁾
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
B[7:0]
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP,
O, LVCMOS
BLUE parallel interface data output pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
Data enable output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
DE
6
O, LVCMOS
control signal pulse width must be 3 PCLKs or longer to be transmitted when the control
signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the control signal filter is disabled
(CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs.
G[7:0]
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP,
O, LVCMOS
GREEN parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
Horizontal sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
HS
8
O, LVCMOS
control signal pulse width must be 3 PCLKs or longer to be transmitted when the control
signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the control signal filter is disabled
(CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs.
(1) 1 = HIGH, 0 = LOW
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