DS90UR905Q-Q1 Datasheet, PDF (45/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
9.2.1.2 Detailed Design Procedure
The DOUT± outputs require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are
placed near the power supply pins. A smaller capacitance capacitor should be located closer to the power supply
pins.
The VODSEL pin is tied to VDDIO for the long cable application. The De-Emph pin may connect a resistor to
ground. Refer to Table 2. The PDB and BISTEN pins are assumed controlling by a microprocessor. The PDB
has to be LOW state until all power supply voltages reach the final voltage. The RFB pin is tied Low to latch data
on the falling edge of the PCLK, High for the rising clock edge. The CNFIG[1:0] pins are set depending on
operating modes and backward compatibility. The SCL, SDA and ID[x] pins are left open when these Serial Bus
Control pins are unused. The RES[2:0] pins and DAP should be tied to ground.
9.2.1.3 Application Curves
Figure 39. Eye Diagram at PCLK = 5 MHz
Figure 40. Eye Diagram at PCLK = 20 MHz
9.2.2 DS90UR906Q-Q1 Typical Connection
Figure 41 shows a typical application of the DS90UR906Q-Q1 deserializer in Pin/STRAP control mode for a 65-
MHz 24-bit Color Display Application. The LVDS inputs utilize 100-nF coupling capacitors to the line and the
receiver provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum,
seven 0.1-µF capacitors and two 4.7-µF capacitors should be used for local device bypassing. System GPO
(General-Purpose Output) signals control the PDB and the BISTEN pins. In this application the RRFB pin is tied
Low to strobe the data on the falling edge of the PCLK.
Since the device in the Pin/STRAP mode, four 10-kΩ pullup resistors are used on the parallel output bus to
select the desired device features. CONFIG[1:0] is set to 01'b for Normal Mode and Control Signal Filter ON, this
is accomplished with the STRAP pullup on B7. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pullups on G4 and G7. To reduce
parallel bus EMI, the SSCG feature is enabled and set to 30 kHz and ±1% with SSC[3:0] set to 0010'b and a
STRAP pullup on R4. The desired features are set with the use of the four pullup resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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