DS90UR905Q-Q1 Datasheet, PDF (32/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
OSC_SEL2
L
L
L
L
H
H
H
H
Table 8. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
OSC_SEL1
L
L
H
H
L
L
H
H
OSC_SEL0
L
H
L
H
L
H
L
H
PCLK OSCILLATOR OUTPUT
Off – Feature Disabled – Default
50 MHz ±40%
25 MHz ±40%
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
8.3 MHz ±40%
6.3 MHz ±40%
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PDB
(DES)
RIN
(Diff.)
active serial stream
X
LOCK
Z
RGB[7:0],
HS, VS, DE L
PCLK*
(DES) L
PASS
Z
L
f
L
H
H
L
Z
L
L
f
L
H
H
L
Z
OFF
Locking
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
Active
OFF
Figure 29. Deserializer Outputs with Output State High and PCLK Output Oscillator Option Enabled
8.3.4.6 Deserializer OP_LOW (Optional)
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. The user
must toggle the OP_LOW Set / Reset register bit to release the outputs to the normal toggling state.
NOTE
The release of the outputs can only occur when LOCK is HIGH. When the OP_LOW
feature is enabled, anytime LOCK = LOW, the LVCMOS outputs will toggle to a LOW
state again. The OP_ LOW strap pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
1. Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state.
Other features should be selected through I²C.
2. OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the
OP_LOW strap value has not been recognized until the DS90UR906Q-Q1 powers up. Figure 30 shows the user
controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31
shows the user controlled release of OP_LOW and manual reset of OP_LOW set.
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