DS90UR905Q-Q1 Datasheet, PDF (35/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
8.3.5.1 Sample BIST Sequence
See Figure 32 for the BIST mode flow diagram.
Step 1: Place the DS90UR905Q-Q1 serializer in BIST Mode by setting serializer BISTEN = H. For the
DS90UR905Q-Q1 serializer or DS99R421 FPD-Link II serializer BIST Mode is enabled through the BISTEN pin.
For the DS90C241 serializer or DS90UR241 serializer, BIST mode is enetered by setting all the input data of the
device to LOW state. A PCLK is required for all the serializer options. When the deserializer detects the BIST
mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off.
Step 2: Place the DS90UR906Q-Q1 deserializer in BIST mode by setting the BISTEN = H. The deserializer is
now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is
detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can
be monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If
there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set Low. The Link returns to normal
operation.
Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 32. BIST Mode Flow Diagram
8.3.5.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the PCLK rate times the test duration. If we
assume a 65-MHz PCLK, a 10 minute (600 seconds) test, and a PASS, the BERT is ≤ 1.07 × 10E-12.
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
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