DS90UR905Q-Q1 Datasheet, PDF (1/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
DS90UR90xQ-Q1 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer
1 Features
•1 5- to 65-MHz PCLK Support (140 Mbps to
1.82 Gbps)
• AC-Coupled STP Interconnect Cable up to 10
Meters
• Integrated Terminations on Serializer and
Deserializer
• At Speed Link BIST Mode and Reporting Pin
• Optional I²C-Compatible Serial Control Bus
• RGB888 + VS, HS, DE Support
• Power Down Mode Minimizes Power Dissipation
• 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
• Automotive-Grade Product: AEC-Q100 Grade 2
Qualified
• >8-kV HBM and ISO 10605 ESD Rating
• Backward Compatible Mode for Operation With
Older Generation Devices
• SERIALIZER — DS90UR905Q-Q1
– RGB888 + VS/HS/DE Serialized to 1 Pair
FPD-Link II
– Randomizer/Scrambler — DC-Balanced Data
Stream
– Selectable Output VOD and Adjustable De-
Emphasis
• DESERIALIZER — DS90UR906Q-Q1
– FAST Random Data Lock; No Reference
Clock Required
– Adjustable Input Receiver Equalization
– LOCK (Real Time Link Status) Reporting Pin
– EMI Minimization on Output Parallel Bus
(SSCG)
– Output Slew Control (OS)
2 Applications
• Automotive Display for Navigation
• Automotive Display for Entertainment
3 Description
The DS90UR90xQ-Q1 chipset translates a parallel
RGB video interface into a high-speed serialized
interface over a single pair. This serial bus scheme
makes system design easy by eliminating skew
problems between clock and data, reducing the
number of connector pins, reducing the interconnect
size, weight, cost, and easing overall PCB layout. In
addition, internal DC-balanced decoding is used to
support AC-coupled interconnects.
The DS90UR905Q-Q1 serializer embeds the clock,
balances the data payload, and level shifts the
signals to high-speed, low voltage differential
signaling. Up to 24 inputs are serialized, along with
the three video control signals. This supports full
24-bit color or 18-bit color and 6 general-purpose
signals (for example, Audio I2S applications).
The DS90UR906Q-Q1 deserializer recovers the data
(RGB) and control signals and extracts the clock from
the serial stream. The DS90UR906Q-Q1 is able to
lock to the incoming data stream without the use of a
training sequence or special SYNC patterns and does
not require a reference clock. A link status (LOCK)
output signal is provided.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UR905Q-Q1 WQFN (48)
7.00 mm × 7.00 mm
DS90UR906Q-Q1 WQFN (60)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HOST
Graphics
Processor
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
BISTEN
Optional
SCL
SDA
ID[x]
Application Diagram
VDDIO
VDDn
(1.8 V or 3.3 V) 1.8 V
VDDn
VDDIO
1.8 V (1.8 V or 3.3 V)
DOUT+
DOUT-
DS90UR905Q
Serializer
DAP
FPD-Link II
1 Pair / AC Coupled
100 nF
100 nF
100 Ω STP Cable
CMF
CONFIG [1:0]
RFB
VODSEL
DeEmph
Optional
PDB
BISTEN
SCL
SDA
ID[x]
RIN+
RIN-
DS90UR906Q
Deserializer
DAP
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
STRAP pins
not shown
RGB Display
QVGA to XGA
24-bit color depth
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.