DS90UR905Q-Q1 Datasheet, PDF (5/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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6 Pin Configuration and Functions
RHS Package
48-Pin WQFN
Top View
DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
G[2] 37
G[3] 38
G[4] 39
G[5] 40
G[6] 41
G[7] 42
B[0] 43
B[1] 44
B[2] 45
B[3] 46
B[4] 47
B[5] 48
DS90UR905Q
TOP VIEW
DAP = GND
24 VODSEL
23 De-Emph
22 VDDTX
21 PDB
20 DOUT+
19 DOUT-
18 RES2
17 VDDHS
16 RES1
15 RES0
14 VDDP
13 CONFIG[1]
DS90UR905Q-Q1 Serializer Pin Functions⁽¹⁾
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
B[7:0]
2, 1, 48, 47, 46, I, LVCMOS BLUE parallel interface data input pins
45, 44, 43
with pulldown (MSB = 7, LSB = 0)
Data enable input
DE
5
I, LVCMOS
with pulldown
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 PCLKs.
G[7:0]
42, 41, 40, 39, I, LVCMOS GREEN parallel interface data input pins
38, 37, 36, 35 with pulldown (MSB = 7, LSB = 0)
Horizontal Sync Input
HS
3
I, LVCMOS
with pulldown
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 PCLKs.
PCLK
10
I, LVCMOS Pixel clock input
with pulldown Latch edge set by RFB function.
R[7:0]
34, 33, 32, 29, I, LVCMOS RED parallel interface data input pins
28, 27, 26, 25 with pulldown (MSB = 7, LSB = 0)
VS
4
I, LVCMOS
with pulldown
Vertical sync input
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
(1) 1 = HIGH, 0 = LOW
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