DS90UR905Q-Q1 Datasheet, PDF (24/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
Functional Block Diagrams (continued)
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CMF
RIN+
RIN-
SSCG
24
RGB [7:0]
HS
VS
DE
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
BISTEN
PDB
SCL
SCA
ID[x]
Timing and
Control
Error
Detector
Clock and
Data
Recovery
PASS
PCLK
LOCK
STRAP INPUT
OP_LOW
Figure 22. DS90UR906Q-Q1 – Deserializer
8.3 Feature Description
8.3.1 Data Transfer
The DS90UR90xQ-Q1 chipset will transmit and receive a pixel of data in the following format: C1 and C0
represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain
the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term
DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data
integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB
coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23
illustrates the serial stream per PCLK cycle.
NOTE
The figure only illustrates the bits but does not actually represent the bit location as the
bits are scrambled and balanced continuously.
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 23. FPD-Link II Serial Stream (DS90UR90xQ-Q1)
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