DS90UR905Q-Q1 Datasheet, PDF (21/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
PCLK
w/ RFB = H
RGB[n],
VS, HS, DE
1/2 V_DDIO
1/2 V_DDIO
1/2 V_DDIO
t_ROS
t_ROH
V_DDIO
GND
V_DDIO
GND
Figure 15. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = On
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data
Bit End
RxIN_TOL
Left
V_TH
0V
RxIN_TOL
Right
V_TL
Ideal Center Position (t_BIT/2)
t_BIT (1 UI)
t_RJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t_RJIT
Figure 16. Receiver Input Jitter Tolerance
BISTEN
PASS
(w/ errors)
Prior BIST Result
Current BIST Test - Toggle on Error
1/2 V_DDIO
t_PASS
1/2 V_DDIO
Result Held
Figure 17. BIST PASS Waveform
SDA
t_f
SCL
t_LOW
t_r
t_f
t_HD;STA
t_SP
t_BUF
t_r
START
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
REPEATED
START
t_SU;STO
STOP START
Figure 18. Serial Control Bus Timing Diagram
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