DS90UR905Q-Q1 Datasheet, PDF (49/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
Layout Guidelines (continued)
11.1.2 LVDS Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S, 2S, 3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
11.2 Layout Example
Figure 44 and Figure 45 show the PCB layout example derived from the layout design of the DS90UR905Q-Q1
and DS90UR906Q-Q1 Evaluation Boards. The graphic and layout description are used to determine both proper
routing and proper solder techniques for designing the board.
Figure 44. DS90UR905Q-Q1 Serializer Example Layout
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