DS90UR905Q-Q1 Datasheet, PDF (34/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
www.ti.com
8.3.4.7 Deserializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the PCLK. If RFB is Low, data is strobed on the Falling edge of the PCLK. This allows for inter-
operability with downstream devices. The deserializer output does not need to use the same edge as the
serializer input. This feature may be controlled by the external pin or by register.
8.3.4.8 Deserializer Control Signal Filter (Optional)
The deserializer provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control
signals and eliminates any pulses that are 1 or 2 PCLKs wide. Control signals must be 3 pixel clocks wide (in its
HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0] or by the Control
Register. This feature may be controlled by the external pin or by Register.
8.3.4.9 Deserializer Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Register.
8.3.4.10 Deserializer Map Select
This feature may be controlled by the external pin or by register.
MAPSEL1
L
L
H
Table 9. Map Select Configuration
INPUTS
MAPSEL0
L
H
H or L
Effect
Bit 4, Bit 5 on LSB
DEFAULT
LSB 0 or 1
LSB 0
8.3.4.11 Deserializer Strap Input Pins
Configuration of the device maybe done through configuration input pins and the STRAP input pins, or through
the Serial Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in
configuration values during the initial power-up sequence of the device. Only a pullup on the pin is required when
a HIGH is desired. By default the pad has an internal pulldown, and will bias Low by itself. The recommended
value of the pullup is 10 kΩ to V_DDIO; open (NC) for Low, no pulldown is required (internal pulldown). If using the
Serial Control Bus, no pullups are required.
8.3.4.12 Optional Serial Bus Control
See Optional Serial Bus Control.
8.3.4.13 Optional BIST Mode
See Built-In Self Test (BIST).
8.3.5 Built-In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the serializer and deserializer BISTEN input pins. The
Ser outputs a test pattern (PRBS7) and drives the link at speed. The deserializer detects the PRBS7 pattern and
monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon
completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power
down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors
were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin.
During the BIST duration the deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1, 2, 3). See
Sample BIST Sequence for entering BIST mode and control.
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