DS90UR905Q-Q1 Datasheet, PDF (43/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
Application Information (continued)
18-BIT RGB
B3
B4
MSB B5
HS
VS
DE
GP0
GP1
GP2
GND
GND
GND
Scenario 3⁽¹⁾
Table 16. Alternate Color / Data Mapping (continued)
18-BIT RGB
G5
GP4
GP5
B0
B1
B2
B3
B4
B5
HS
VS
DE
Scenario 2⁽²⁾
24-BIT RGB
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
Scenario 1⁽³⁾
905 PIN NAME 906 PIN NAME
G7
G7
B0
B0
B1
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
HS
HS
VS
VS
DE
DE
905 Pin Name 906 Pin Name
24-BIT RGB
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
Scenario 1⁽³⁾
18-BIT RGB
G5
GP4
GP5
B0
B1
B2
B3
B4
B5
HS
VS
DE
Scenario 2⁽²⁾
18-BIT RGB
B3
B4
MSB B5
HS
VS
DE
GP0
GP1
GP2
GND
GND
GND
Scenario 3⁽¹⁾
(1) Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general-purpose signals.
(2) Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general-purpose signals.
(3) Scenario 1 supports the 24-bit RGB color mapping, along with the 3 embedded video control signals. This is the native mode for the
chipset.
9.2 Typical Applications
9.2.1 DS90UR905Q-Q1 Typical Connection
Figure 38 shows a typical application of the DS90UR905Q-Q1 serializer in Pin control mode for a 65 MHz 24-bit
Color Display Application. The LVDS outputs require 100-nF AC-coupling capacitors to the line. The line driver
includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1
µF capacitors and a 4.7-µF capacitor should be used for local device bypassing. System GPO (General-Purpose
Output) signals control the PDB and BISTEN pins. In this application the RFB pin is tied Low to latch data on the
falling edge of the PCLK. The application assumes the companion deserializer (DS90UR906Q-Q1) therefore the
configuration pins are also both tied Low. In this example the cable is long, therefore the VODSEL pin is tied
High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8-V LVCMOS
levels, thus the VDDIO pin is connected also to the 1.8-V rail. The Optional Serial Bus Control is not used in this
example, thus the SCL, SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
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