DS90UR905Q-Q1 Datasheet, PDF (15/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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Timing Requirements for Serial Control Bus (continued)
over 3.3-V supply and temperature ranges unless otherwise specified.
TEST CONDITIONS
t_SU;STO
Set-up time for STOP condition, ^{Standard Mode}
Figure 18
Fast Mode
t_BUF
Bus free time between STOP
and START, Figure 18
Standard Mode
Fast Mode
t_r
SCL and SDA rise time,
Figure 18
Standard Mode
Fast Mode
t_f
SCL and SDA fall time,
Figure 18
Standard Mode
Fast mode
DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
MIN NOM MAX UNIT
4
µs
0.6
µs
4.7
µs
1.3
µs
1000 µs
300 ns
300 ns
300 ns
7.11 Switching Characteristics: Serializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS
TEST CONDITIONS
t_LHT
Serializer output low-to-high
transition time, Figure 3
R_L = 100 Ω, De-emphasis = disabled, VODSEL = 0
R_L = 100 Ω, De-emphasis = disabled, VODSEL = 1
t_HLT
Serializer output high-to-low
transition time, Figure 3
R_L = 100 Ω, De-emphasis = disabled, VODSEL = 0
R_L = 100 Ω, De-emphasis = disabled, VODSEL = 1
t_DIS
Input data – set-up time,
Figure 4
RGB[7:0], HS, VS, DE to PCLK
t_DIH
Input data – hold time,
Figure 4
PCLK to RGB[7:0], HS, VS, DE
t_XZD
Serializer output active to OFF
delay, Figure 6⁽¹⁾
t_PLD ⁽²⁾
Serializer PLL lock time,
Figure 5⁽¹⁾⁽³⁾
R_L = 100 Ω
t_SD
Serializer delay – latency,
Figure 7⁽¹⁾
R_L = 100 Ω
R_L = 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 65 MHz
t_DJIT
Serializer output total jitter,
Figure 8
R_L = 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 43 MHz
R_L = 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 5 MHz
PCLK = 65 MHz
λ_STXBW
Serializer jitter transfer
Function –3-dB bandwidth
PCLK = 43 MHz
PCLK = 20 MHz
PCLK = 5 MHz
PCLK = 65 MHz
δ_STX
Serializer jitter transfer
function peaking
PCLK = 43 MHz
PCLK = 20 MHz
PCLK = 5 MHz
MIN TYP MAX UNIT
200
ps
200
ps
200
ps
200
ps
2
ns
2
ns
8
15 ns
1.4
10 ms
144 × T 145 × T ns
0.28
UI ⁽⁴⁾
0.27
UI
0.35
3
2.3
1.3
650
0.838
0.825
0.826
0.278
UI
MHz
MHz
MHz
kHz
dB
dB
dB
dB
(1) Specification is ensured by characterization and is not tested in production.
(2) t_PLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) When the serializer output is at TRI-STATE the deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require t_PLD
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / [28 × PCLK]). The UI scales with PCLK frequency.
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