DS90UR905Q-Q1 Datasheet, PDF (6/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
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DS90UR905Q-Q1 Serializer Pin Functions⁽¹⁾ (continued)
NAME
PIN
NO.
I/O, TYPE
CONTROL AND CONFIGURATION
BISTEN
31
I, LVCMOS
with pulldown
CONFIG[1:0]
13, 12
I, LVCMOS
with pulldown
De-Emph
ID[x]
23
I, Analog
with pullup
6
I, Analog
PDB
21
I, LVCMOS
with pulldown
RES[2:0]
RFB
18, 16, 15
11
I, LVCMOS
with pulldown
I, LVCMOS
with pulldown
SCL
SDA
8
I, LVCMOS
9
I/O, LVCMOS
Open-Drain
VODSEL
24
I, LVCMOS
with pulldown
FPD-LINK II SERIAL INTERFACE
DOUT+
20
O, LVDS
DOUT-
19
POWER AND GROUND⁽²⁾
GND
DAP
VDDHS
17
VDDL
7
VDDP
14
VDDIO
30
VDDTX
22
O, LVDS
Ground
Power
Power
Power
Power
Power
DESCRIPTION
BIST mode — optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
Operating modes — pin or register control
Determine the operating mode of the DS90UR905 and interfacing device.
CONFIG[1:0] = 00: interfacing to DS90UR906Q-Q1, control signal filter DISABLED
CONFIG[1:0] = 01: interfacing to DS90UR906Q-Q1, control signal filter ENABLED
CONFIG[1:0] = 10: interfacing to DS90UR124, DS99R124
CONFIG[1:0] = 11: interfacing to DS90C124
De-emphasis control — pin or register control
De-emph = open (float) - disabled
To enable de-emphasis, tie a resistor from this pin to GND or control via register (see
Table 2).
Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩ pullup to 1.8-V rail (see Table 11).
Power-down mode input
PDB = 1, serializer is enabled (normal operation).
Refer to Power Up Requirements and PDB Pin.
PDB = 0, serializer is powered down
When the serializer is in the power-down state, the driver outputs (DOUT±) are both
logic high, the PLL is shutdown, IDD is minimized. Control registers are RESET.
Reserved - tie LOW
Pixel clock input latch edge select — pin or register control
RFB = 1, parallel interface data and control signals are latched on the rising clock
edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock
edge.
Serial control bus clock input - optional
SCL requires an external pullup resistor to V_DDIO.
Serial control bus data input/output - optional
SDA requires an external pullup resistor V_DDIO.
Differential driver output voltage select — pin or register control
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typical) — long cable / de-emp
applications
VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typical)
True output
The output must be AC-coupled with a 100-nF capacitor.
Inverting output
The output must be AC-coupled with a 100-nF capacitor.
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
TX high-speed logic power, 1.8 V ±5%
Logic power, 1.8 V ±5%
PLL power, 1.8 V ±5%
LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10%
Output Driver power, 1.8 V ±5%
(2) The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
6
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