DS90UR905Q-Q1 Datasheet, PDF (25/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
Feature Description (continued)
8.3.2 Video Control Signal Filter — Serializer and Deserializer
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK
or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals (see Figure 24).
PCLK
IN
HS/VS/DE
IN
PCLK
OUT
Latency
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 24. Video Control Signal Filter Waveform
8.3.3 Serializer Functional Description
The serializer converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the FPD-Link II data coding that
provides randomization, scrambling, and DC balancing of the video data. The serializer includes multiple features
to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data and also the system spread spectrum PCLK support. The serializer features power saving features with a
sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
8.3.3.1 EMI Reduction Features
8.3.3.1.1 Serializer Spread Spectrum Compatibility
The serializer PCLK is capable of tracking spread spectrum clocking (SSC) from a host source. The PCLK will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the PCLK input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
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