DS90UR905Q-Q1 Datasheet, PDF (16/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
www.ti.com
7.12 Switching Characteristics: Deserializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS
TEST CONDITIONS
PIN / FREQ
t_RCP
PCLK output period
t_RCP = t_TCP
SSCG=OFF, 5–65 MHz
PCLK
t_RDC
PCLK output duty cycle
SSCG=ON, 5–20 MHz
SSCG=ON, 20–65 MHz
PCLK
LVCMOS
V_DDIO = 1.8 V, C_L = 4 pF
t_CLH
Low-to-high transition time,
Figure 10
V_DDIO = 3.3 V, C_L = 4 pF
PCLK/RGB[7:0], HS,
VS, DE
t_CHL
t_ROS
t_ROH
t_DDLT ⁽¹⁾
LVCMOS
High-to-low transition time,
Figure 10
Data valid before PCLK –
set-up time Figure 14
Data valid after PCLK – hold
time Figure 14
Deserializer lock time,
Figure 13
V_DDIO = 1.8 V
C_L = 4 pF, OS_PCLK/DATA = L
V_DDIO = 3.3 V
C_L = 4 pF, OS_PCLK/DATA = H
V_DDIO = 1.71 to 1.89 V or 3.0 to
3.6 V
C_L = 4pF (lumped load)
V_DDIO = 1.71 to 1.89 V or 3.0 to
3.6 V
C_L = 4pF (lumped load)
SSC[3:0] = 0000 (OFF)⁽²⁾
SSC[3:0] = 0000 (OFF)⁽²⁾
SSC[3:0] = ON⁽²⁾
SSC[3:0] = ON⁽²⁾
PCLK/RGB[7:0], HS,
VS, DE
RGB[7:0], HS, VS, DE
RGB[7:0], HS, VS, DE
PCLK = 5 MHz
PCLK = 65 MHz
PCLK = 5 MHz
PCLK = 65 MHz
t_DD
Deserializer delay – latency,
Figure 11
SSC[3:0] = 0000 (OFF)⁽²⁾
t_DPJ
Deserializer period jitter
SSC[3:0] = OFF^(3)(4)(5)
PCLK = 5 MHz
PCLK = 10 MHz
PCLK = 65 MHz
t_DCCJ
Deserializer cycle-to-cycle
jitter
SSC[3:0] = OFF^(6)(7)(5)
PCLK = 5 MHz
PCLK = 10 MHz
PCLK = 65 MHz
t_IJT
Deserializer input jitter
tolerance, Figure 16
EQ = OFF,
SSCG = OFF,
PCLK = 65 MHz
for jitter freq < 2 MHz
for jitter freq > 6 MHz
BIST Mode
t_PASS
BIST PASS valid time,
BISTEN = 1, Figure 17
SSCG Mode
f_DEV
Spread spectrum clocking
deviation frequency
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
f_MOD
Spread spectrum clocking
modulation frequency
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
MIN
15.38
43%
35%
40%
TYP
T
50%
59%
53%
2.1
2.0
1.6
1.5
MAX
200
57%
65%
60%
UNIT
ns
ns
ns
ns
ns
0.27 0.45
T
0.4 0.55
T
3
ms
4
ms
30
ms
6
ms
139 × T 140 × T ns
975 1700 ps
500 1000 ps
550 1250 ps
675 1150 ps
375
900 ps
500 1150 ps
0.9
UI
0.5
UI
1
10 µs
±0.5%
8
±2%
100 kHz
(1) t_DDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) t_PLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) t_DPJ is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) Specification is ensured by characterization and is not tested in production.
(7) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
16
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