DS90UR905Q-Q1 Datasheet, PDF (8/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
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DS90UR906Q-Q1 Deserializer Pin Functions⁽¹⁾ (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
LOCK
LOCK status output
32
O, LVCMOS
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS, VS,
DE and PCLK output states are controlled by OSS_SEL (see Table 6). May be used as link
status or to flag when video data is active (ON/OFF).
PASS
PASS output (BIST mode)
42
O, LVCMOS
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
PCLK
Pixel clock output
5
O, LVCMOS In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Strobe
edge set by RFB function.
R[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP,
O, LVCMOS
RED parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
Vertical sync output
VS
7
O, LVCMOS
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
CONTROL AND CONFIGURATION — STRAP PINS
For a HIGH state, use a 10-kΩ pullup to V_DDIO; for a LOW state, the IO includes an internal pulldown. The STRAP pins are read upon
power up and set device configuration. Pin Number listed along with shared RGB output name in square brackets.
CONFIG[1:0]
10 [B6],
9 [B7]
Operating modes — pin or register control
STRAP
I, LVCMOS
with pulldown
These pins determine the operating mode of the DS90UR906 and interfacing device.
CONFIG[1:0] = 00: interfacing to DS90UR905Q-Q1, control signal filter DISABLED
CONFIG[1:0] = 01: interfacing to DS90UR905Q-Q1, control signal filter ENABLED
CONFIG[1:0] = 10: interfacing to DS90UR241
CONFIG[1:0] = 11: interfacing to DS90C241
EQ[3:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP
I, LVCMOS Receiver input equalization — pin or register control (see Table 3).
with pulldown
LF_MODE
12 [B4]
STRAP
I, LVCMOS
with pulldown
SSCG low-frequency mode — pin or register control
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low-frequency mode (PCLK = 5 to 20 MHz)
LF_MODE = 0, SSCG in high-frequency mode (PCLK = 20 to 65 MHz)
MAP_SEL[1:0]
40 [R1],
41 [R0]
STRAP
I, LVCMOS
with pulldown
Bit mapping backward compatibility / DS90UR241 options — pin or register control
Normal setting to b'00 (see Table 9).
OP_LOW
42 PASS
STRAP
I, LVCMOS
with pulldown
Outputs held LOW when LOCK = 1 — pin or register control
See ⁽²⁾
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release / set register HIGH
See ⁽³⁾
See Figure 30 and Figure 31.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OS_DATA
14 [B3]
STRAP Data output slew select — pin or register control
I, LVCMOS OS_DATA = 1, increased DATA slew
with pulldown OS_DATA = 0, normal (default)
OSC_SEL[2:0]
26 [G2],
27 [G1],
28 [G0]
STRAP
I, LVCMOS Oscillator select — pin or register control (see Table 7 and Table 8).
with pulldown
OS_PCLK
11 [B5]
STRAP PCLK output slew select — pin or register control
I, LVCMOS OS_PCLK = 1, increased PCLK slew
with pulldown OS_PCLK = 0, normal (default)
OSS_SEL
17 [B2]
STRAP
I, LVCMOS
with pulldown
Output sleep state select — pin or register control
See ⁽⁴⁾
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power
down (Sleep) (see Table 6).
(2) It is not recommended to use any other strap options with this strap function
(3) Before the device is powered up, the outputs are in tri-state.
(4) OSS_SEL strap cannot be used if OP_LOW =1
8
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