DS90UR905Q-Q1 Datasheet, PDF (47/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

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DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
9.2.2.1 Design Requirements
For this example, use the parameters listed in Table 18.
Table 18. Design Parameters
DESIGN PARAMETERS
VDDIO
VDDL, VDDSC, VDDPR, VDDR,
VDDIR, VDDCMLO
AC-Coupling Capacitor for DOUT±
EXAMPLE VALUE
1.8 V to 3.3 V
1.8 V
100 nF
9.2.2.2 Detailed Design Procedure
The RIN± input require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are placed
near the power supply pins. A smaller capacitance capacitor should be located closer to the power supply pins.
The device has twenty-two Control and Configuration pins which are called STARTP pins. These pins include an
internal pulldown. For a HIGH state, use a 10-KΩ resistor pulled up to VDDIO.
The PDB and BISTEN pins are assumed controlling by a microprocessor. The PDB has to be LOW state until all
power supply voltages reach the final voltage. The SCL, SDA and ID[x] pins are left open when these Serial Bus
Control pins are unused.
The RES pins and DAP should be tied to ground.
9.2.2.3 Application Curves
Figure 42. Eye Diagram at PCLK = 45 MHz
Figure 43. Eye Diagram at PCLK = 65 MHz
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