DS90UR905Q-Q1 Datasheet, PDF (42/58 Pages) Texas Instruments – 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer

DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313H – SEPTEMBER 2009 – REVISED JULY 2015
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Display Application
The DS90UR90xQ-Q1 chipset is intended for interface between a host (graphics processor) and a display. It
supports an 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888 application, 24
color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general-purpose signals may also be sent from host to display.
The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is
expected to be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge
sensitive and strobes the data. It is also assumed that the fanout of the deserializer is one. If additional loads
need to be driven, a logic buffer or mux device is recommended.
9.1.2 Live Link Insertion
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug & go” hot insertion capability allows the DS90UR906Q-Q1 to attain lock to the active data
stream during a live insertion event.
9.1.3 Alternate Color / Data Mapping
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit Color Applications.
Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While this is recommended it is not
required. When connecting to earlier generations of FPD-Link II serializer and deserializer devices, a color
mapping review is recommended to ensure the correct connectivity is obtained. Table 16 provides examples for
interfacing to 18-bit applications with or without the video control signals embedded. The DS90UR906Q-Q1
deserializer also provides additional flexibility with the MAP_SEL feature as well.
18-BIT RGB
LSB R0
R1
R2
R3
R4
MSB R5
LSB G0
G1
G2
G3
G4
MSB G5
LSB B0
B1
B2
18-BIT RGB
GP0
GP1
R0
R1
R2
R3
R4
R5
GP2
GP3
GO
G1
G2
G3
G4
Table 16. Alternate Color / Data Mapping
24-BIT RGB
RO
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
905 PIN NAME 906 PIN NAME
RO
R0
R1
R1
R2
R2
R3
R3
R4
R4
R5
R5
R6
R6
R7
R7
G0
G0
G1
G1
G2
G2
G3
G3
G4
G4
G5
G5
G6
G6
24-BIT RGB
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
18-BIT RGB
GP0
GP1
R0
R1
R2
R3
R4
R5
GP2
GP3
G0
G1
G2
G3
G4
18-BIT RGB
LSB R0
R1
R2
R3
R4
MSB R5
LSB G0
G1
G2
G3
G4
MSB G5
LSB0
B1
B2
42
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