DS125RT410_15 Datasheet, PDF (9/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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7 Detailed Description
DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
7.1 Overview
The DS125RT410 is a multi-rate, 4-channel retimer. Each channel in the DS125RT410 operates independently.
All channels include a continuous time linear equalizer (CTLE), clock and data recovery circuit (CDR) and a
differential driver with programmable output voltage and de-emphasis. Each channel also has its own eye
opening monitor (EOM) and configurable pseudo-random bit sequence (PRBS) pattern generator that can be
used for debug purposes.
The DS125RT410 is configurable through a single SMBus port. The DS125RT410 can also act as an SMBus
master to configure itself from an EEPROM.
The following sections describe the functionality of the various circuits and features within the DS125RT410.
7.2 Functional Block Diagram
IN+
IN-
100:
CTLE
Signal
Detect
Retimer/CDR
Eye
Opening
Monitor
Patt.
Gen
Driver with
De-emphasis
100
OUT+
OUT-
REFCLK_IN
SMBus
2.5V
Digital Core
VCO
1.2V
Regulator
2V
Regulator
Figure 3. DS125RT410 Data Path Block Diagram — One of Four Channels
7.3 Feature Description
7.3.1 Device Data Path Operation
The data path operation of the DS125RT410 comprises with the functional sections as listed in the data path
block diagram of Figure 3. The functional sections are as follows.
• Signal Detect
• CTLE
• CDR
• Differential Driver with De-emphasis
7.3.2 Signal Detect
The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high
speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to
automatically power on or off the rest of the high speed data path depending on if a signal is present. The signal
detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired
manually force channels to be disabled.
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