DS125RT410_15 Datasheet, PDF (50/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
Typical Application (continued)
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Figure 9. Typical Output Eye Diagram for the DS125RT410
Operating at 10.3125 Gbps With Default VOD of 600 mVp-p
and De-emphasis Setting of –2 dB
Figure 10. Example of TX De-emphasis for a DS125RT410
Operating at 10.3125 Gbps
9 Power Supply Recommendations
Figure 11 depicts an example power connections diagram for the DS125RT410. The supply (VDD) and ground
(GND) Pins should be connected to power planes routed on adjacent layers of the printed circuit board. The
layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance
supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of
bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each VDD Pin such that the
capacitor is placed as close as possible to the DS125RT410. Smaller body size capacitors can help facilitate
proper component placement. Additionally, capacitor with capacitance in the range of 1 µF to 10 µF should be
incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-
low ESR ceramic.
Figure 11. Example Power Connections Diagram for the DS125RT410
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