DS125RT410_15 Datasheet, PDF (36/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
www.ti.com
Table 15. Channel Registers (continued)
ADDRESS
(HEX)
8
9
A
B
C
D
E
F
BITS
7:5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7:4
3
2
1
0
7:6
5
4:0
7:0
7:0
DEFAULT
VALUE
(Hex)
0
0
0
0
0
0
0
0
0
MODE
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0x93
RW
0x69
RW
EEPROM
FIELD NAME
DESCRIPTION
Y
RESERVED
Y
CDR_CAP_DAC_START4
Starting VCO Cap Dac Setting 0
Y
CDR_CAP_DAC_START3
Starting VCO Cap Dac Setting 0
Y
CDR_CAP_DAC_START2
Starting VCO Cap Dac Setting 0
Y
CDR_CAP_DAC_START1
Starting VCO Cap Dac Setting 0
Y
CDR_CAP_DAC_START0
Starting VCO Cap Dac Setting 0
Y
DIVSEL_VCO_CAP_OV
Enable bit to override cap_cnt with value in register 0x0B[4:0]
Y
SET_CP_LVL_LPF_OV
Enable bit to override lpf_dac_val with value in register 0x1F[4:0]
Y
BYPASS_PFD_OV
Enable bit to override sel_retimed_loopthru and sel_raw_loopthru
with values in reg 0x1E[7:5]
Y
EN_FD_PD_VCO_PDIQ_OV Enable bit to override en_fd, pd_pd, pd_vco, pd_pdiq with reg
0x1E[0], reg 0x1E[2], reg 0x1C[0], reg 0x1C[1]
Y
EN_PD_CP_OV
Enable bit to override pd_fd_cp and pd_pd_cp with value in reg
0x1B[1:0]
Y
DIVSEL_OV
Enable bit to override divsel with value in reg 0x18[6:4]
1: Override enable
0: Normal operation
Y
EN_FLD_OV
Enable to override pd_fld with value in reg 0x1E[1]
Y
PFD_LOCK_MODE_SM
Enable FD in lock state
Y
SBT_EN
Enable bit to override sbt_en with value in reg 0x1D[7]
Y
EN_IDAC_PD_CP_OV
Enable bit to overridephase detector charge pump settings with reg
0x1C[7:5]
EN_IDAC_FD_CP_OV
Enable bit to override frequency detector charge pump settings with
reg 0x1C[4:2]
Y
DAC_LPF_HIGH_PHASE_OV Enable bit to override loop filter comparator trip voltage with reg
DAC_LPF_LOW_PHASE_OV ^0x16[7:0]
Y
EN150_LPF_OV
Enable bit to override en150_lpf with value in reg 0x1F[6]
N
CDR_RESET_OV
Enable bit to override CDR reset with reg 0x0A[2]
N
CDR_RESET_SM
1: CDR is put into reset
0: normal CDR operation
N
CDR_LOCK_OV
Enable CDR lock signal override with reg 0x0A[0]
N
CDR_LOCK
CDR lock signal override bit
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
CAP_DAC_START1[4]
Starting VCO cap dac setting 1
Y
CAP_DAC_START1[3]
Starting VCO cap dac setting 1
Y
CAP_DAC_START1[2]
Starting VCO cap dac setting 1
Y
CAP_DAC_START1[1]
Starting VCO cap dac setting 1
Y
CAP_DAC_START1[0]
Starting VCO cap dac setting 1
N
RESERVED
Y
SINGLE_BIT_LIMIT_CHECK_ 1: Normal operation, device checks for single bit transitions as a gate
ON
to achieving CDR lock
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
PRBS_PATT_SHIFT_EN
PRBS Generator Clock Enable
• 1: Enabled
• 0: Disabled
Y
RESERVED
N
RESERVED
N
RESERVED
36
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