DS125RT410_15 Datasheet, PDF (1/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
DS125RT410 Low-Power Multi-Rate Quad Channel Retimer
1 Features
•1 Each Channel Independently Locks to Data Rates
From 9.8 to 12.5 Gbps and Submultiples
• Fast Lock Operation Based on Protocol-Select
Mode
• Low Latency (≈300 ps)
• Adaptive Equalization up to 34-dB Boost at 5 GHz
• Adjustable Transmit V_OD: 600 to 1300 mVp-p
• Adjustable Transmit De-emphasis to –15 dB
• Typical Power Dissipation (EQ+CDR+DE):
150 mW/Channel
• Programmable Output Polarity Inversion
• Input Signal Detection, CDR Lock Detection and
Indicator
• On-Chip Eye Monitor (EOM), PRBS Generator
• Single 2.5-V ± 5% Power Supply
• SMBus and EEPROM Configuration Modes
• Operating Temperature Range of –40 to 85°C
• WQFN 48-Pin 7-mm × 7-mm Package
• Easy Pin Compatible Upgrade Between Repeater
and Retimers
– DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
– DS100DF410 (EQ+DFE+CDR+DE):
10.3125 Gbps
– DS110RT410 (EQ+CDR+DE): 8.5 to
11.3 Gbps
– DS110DF410 (EQ+DFE+CDR+DE): 8.5 to
11.3 Gbps
– DS125RT410 (EQ+CDR+DE): 9.8 to
12.5 Gbps
– DS125DF410 (EQ+DFE+CDR+DE):
9.8 to 12.5 Gbps
– DS100BR410 (EQ+DE): Up to 10.3125 Gbps
2 Applications
• Front Port SFF 8431 (SFP+) Optical and Direct
Attach Copper
• Backplane Reach Extension, Data Retimer
• Ethernet: 10 GbE, 1 GbE
• CPRI: Line Bit Rate Options 3–7
• Interlaken: All Lane Bit Rates
• InfiniBand
• Other Propriety Data Rates up to 12.5 Gbps
3 Description
The DS125RT410 is a four-channel retimer with
integrated signal conditioning. The device includes a
fully adaptive continuous-time linear equalizer
(CTLE), clock and data recovery (CDR), and a
transmit de-emphasis (DE) driver to enable data
transmission over long, lossy and crosstalk-impaired
highspeed serial links to achieve BER < 1 × 10^–15.
For channels with a high amount of crosstalk, the
DS125DF410 should be used because it has self
calibrating 5-tap decision-feedback equalizer (DFE).
Each channel can independently lock to data rate
from 9.8 to 12.5 Gbps, and associated subrates
(divide by 2, 4, and 8) to support a variety of
communication protocols. A 25-MHz crystal oscillator
clock is used to speed up the CDR lock process. This
clock is not used for training the PLL and does not
need to be synchronous with the serial data.
The programmable settings can be applied using the
SMBus (I2C) interface, or they can be loaded through
an external EEPROM. An on-chip eye monitor and a
PRBS generator allow real-time measurement of
high-speed serial data for system bring-up or field
tuning.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS125RT410
WQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
Switch Fabric
Line Card
DS125DF410
Optical Modules
x4
ASIC
x4
x4
10GbE
CPRI
SFP+ (SFF8431)
ASIC
Interlaken
QSFP
Others
Back
Plane/
Mid
Plane
x4
DS125DF410
Passive Copper
Clean Signal
Noisy Signal
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.