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DS125RT410_15 Datasheet, PDF (19/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer
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DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
7.5 Programming
• SMBus Master Configuration Mode
• SMBus Slave Configuration Mode
The configuration mode is selected by the state of the SMBus Enable pin (pin 20) when the DS125RT410 is
powered-up. This pin should be either left floating or tied to the device VDD through an optional 1-kΩ resistor. The
effect of each of these settings is listed in Table 4.
Table 4. SMBus Enable Settings
PIN
SETTING
Float
High (1)
CONFIGURATION
MODE
DESCRIPTION
SMBus Master Mode
Device reads its configuration from an external
EEPROM on power-up.
SMBus Slave Mode
Device is configured over the SMBus by an external
controller.
READ_EN PIN
Pull low to initiate reading configuration data
from external EEPROM
Tie low to enable proper address strapping on
power-up
7.5.1 SMBus Strap Observation
Register 0x00, bits 7:4 and register 0x06, bits 3:0
In order to communicate with the DS125RT410 over the SMBus, it is necessary for the SMBus controller to know
the address of the DS125RT410. The address strap observation bits in control/shared register 0x00 are primarily
useful as a test of SMBus operation. There is no way to get the DS125RT410 to indicate what its SMBus
address is unless it is already known.
In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the
diagnostic test control bits of control/shared register 0x06. This four-bit field should be written with a value of 0xa.
When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps
can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the
ADDR3:ADDR0 lines when the DS125RT410 was powered up. For example, if a value of 0x1 is read from
control/shared register 0x00, bits 7:4, then at power-up the ADDR0 line was set to 1 and the other address lines,
ADDR3:ADDR1, were all set to 0. The DS125RT410 is set to an SMBus Write address of 0x32.
7.5.2 Device Revision and Device ID
Register 0x01
Control/shared register 0x01 contains the device revision and device ID. The device revision listed in Table 13 is
the current revision for the DS125RT410. The device ID will be different for the different devices in the retimer
family. This register is useful because it can be interrogated by software to determine the device variant and
revision installed in a particular system. The software might then configure the device with appropriate settings
depending upon the device variant and revision.
7.5.3 Control/Shared Register Reset
Register 0x04, bit 6
Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self-clearing,
so it is cleared after it is written and the control/shared registers are reset to their factory default values.
7.5.4 Interrupt Channel Flag Bits
Register 0x05, bits 3:0
The operation of these bits is described in Interrupt Status.
7.5.5 SMBus Master Mode Control Bits
Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4
Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the
DS125RT410 is in SMBus slave mode. This is an undefined condition.
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Product Folder Links: DS125RT410
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