DS125RT410_15 Datasheet, PDF (20/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
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When this bit is set, if the EN_SMB pin is floating (meaning that the DS125RT410 is in SMBus master mode),
then the DS125RT410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This
bit is not self-clearing, so it should be cleared after it is set.
When the DS125RT410 EN_SMB pin is floating (meaning that the DS125RT410 is in SMBus master mode), it
will read from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is
complete, register 0x05, bit 4 will be set. Alternatively, the DS125RT410 will read from its external EEPROM
when triggered by register 0x04, bit 4, as described in the following.
When register 0x04, bit 4, is set, the DS125RT410 reads its configuration from an external EEPROM over the
SMBus immediately. When this bit is set, the DS125RT410 does not wait until the READ_EN pin is pulled low to
read from the EEPROM. This EEPROM read occurs whether the DS125RT410 is in SMBus master mode or not.
If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the
DS125RT410 may hang up and a power-up reset may be necessary to return it to proper operation. You should
only set this bit if you know that the EEPROM is present and properly configured.
If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause
the DS125RT410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the
SMBus master mode. If the DS125RT410 is not in SMBus master mode, do not set this bit. After setting this bit,
it should be cleared before further SMBus operations.
After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN
pin low or by then setting register 0x04, bit 4.
Register 0x05, bit 7, disables SMBus master mode. This prevents the DS125RT410 from trying to take command
of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has
already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in
which disabling EEPROM master mode read is valid are (1) when the DS125RT410 is in SMBus master mode,
but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus
master mode but the EEPROM read operation has not yet occurred.
Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the
DS125RT410 to hang up.
7.5.6 Resetting Individual Channels of the Retimer
Register 0x00, bit 2, and register 0x0a, bits 3:2
Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory
default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the
DS125RT410 since it was powered-up.
To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and
adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the
reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same
operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal
is present at the input to the selected channel, the DS125RT410 will attempt to lock to it and will adapt its CTLE
according to the currently configured adapt mode for the selected channel. The adapt mode is configured by
channel register 0x31, bits 6:5.
7.5.7 Interrupt Status
Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and
Register 0x36, bit 6
Each channel of the DS125RT410 will generate an interrupt under several different conditions. The DS125RT410
will always generate an interrupt when it loses CDR lock or when a signal is no longer detected at its input. If the
HEO/VEO interrupt is enabled by setting bit 6 of register 0x36, then the retimer will generate an interrupt when
the horizontal or vertical eye opening falls below the preset values even if the retimer remains locked. When one
of these interrupt conditions occurs, the retimer alerts the system controller via hardware and provides additional
details via register reads over the SMBus.
First, the open-drain interrupt line INT is pulled low. This indicates that one or more of the channels of the retimer
has generated an interrupt. The interrupt lines from multiple retimers can be wire-ANDed together so that if any
retimer generates an interrupt the system controller can be notified using a single interrupt input.
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