DS125RT410_15 Datasheet, PDF (28/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
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12. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine.
13. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring.
7.5.14 Enabling Slow Rise and Fall Time on the Output Driver
Register 0x18, bit 2
Normally the rise and fall times of the output driver of the DS125RT410 are set by the slew rate of the output
transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence
the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For
example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by
a system.
Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.
Setting this bit will approximately double the nominal rise and fall times of the DS125RT410 output driver. This bit
is cleared by default.
7.5.15 Inverting the Output Polarity
Register 0x1f, bit 7
In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes
necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.
The DS125RT410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of
register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility
in system design and board layout.
7.5.16 Overriding the Figure of Merit for Adaptation
Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e,
bits 7 and 6
The default figure of merit for the CTLE adaptation in the DS125RT410 is simple. The horizontal and vertical eye
openings are measured for each CTLE boost setting. The vertical eye opening is scaled to a constant reference
vertical eye opening and the smaller of the horizontal or vertical eye opening is taken as the figure of merit for
that set of equalizer settings. The objective is to adapt the equalizer to a point where the horizontal and vertical
eye openings are both as large as possible. This usually provides optimum bit error rate performance for most
transmission channels.
In some systems the adaptation can reach a better setting if only the horizontal or vertical eye opening is used to
compute the figure of merit rather than using both. This will be system-dependent and the user must determine
through experiment whether this provides better adaptation in the user's system.
The CTLE figure of merit type is selected using the two-bit field in register 0x31, bits 4:3.
For some transmission media the adaptation can reach a better setting if a different figure of merit is used. The
DS125RT410 includes the capability of adapting based on a configurable figure of merit. The configurable figure
of merit is structured as listed in Equation 7.
FOM = (HEO – b) × a + (VEO – c) × (1 – a)
(7)
In this equation, HEO is horizontal eye opening, VEO is vertical eye opening, FOM is the figure of merit, and the
factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively.
In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of
merit for the CTLE adaptation, set bit 7 of register 0x6e, the en_new_fom_ctle bit.
7.5.17 Setting the Rate and Subrate for Lock Acquisition
Register 0x2f, bits 7:6 and 5:4
The rate and subrate settings, which constrain the data rate search in order to reduce lock time, can be set using
channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>. These four bits form a hex digit
which matches the codes in Table 2.
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