DS125RT410_15 Datasheet, PDF (4/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
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Pin Functions (continued)
PIN
I/O, TYPE ⁽¹⁾
NAME
NO.
DESCRIPTION
LOOP FILTER CONNECTION PINS
LPF_CP_0
LPF_REF_0
47
48
I/O, analog
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_0 and LPF_REF_0
LPF_CP_1
LPF_REF_1
38
37
I/O, analog
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_1 and LPF_REF_1
LPF_CP_2
LPF_REF_2
23
24
I/O, analog
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_2 and LPF_REF_2
LPF_CP_3
LPF_REF_3
14
13
I/O, analog
Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_3 and LPF_REF_3
REFERENCE CLOCK I/O
REFCLK_IN
19
I, 2.5-V analog
Input is 2.5 V, 25 MHz ± 100-ppm reference clock from external oscillator
No stringent phase noise requirement
REFCLK_OUT
42
O, 2.5-V
analog
Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS125RT410
devices on a board
LOCK INDICATOR PINS
LOCK0
LOCK1
LOCK2
LOCK3
45
40
O, 2.5-V Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding channel.
21
LVCMOS These pins are shared with SMBus address strap input functions read at start-up.
16
SMBus MASTER MODE PINS
ALL_DONE
41
O, 2.5-V
LVCMOS
Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has been
completed.
READ_EN
44
I, 2.5-V
LVCMOS
Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The
READ_EN pin must be tied low when in SMBus slave mode.
INTERRUPT OUTPUT
INT
43
O, 3.3-V
LVCMOS,
Open Drain
Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect, or
CDR unlock.
External 2-kΩ to 5-kΩ pullup resistor is required.
Pin is 3.3-V LVCMOS tolerant.
SERIAL MANAGEMENT BUS (SMBus) INTERFACE
EN_SMB
Input is 2.5 V, selects SMBus master mode or SMBus slave mode.
20
I, 2.5-V analog
EN_SMB = High for slave mode
EN_SMB = Float for master mode
Tie READ_EN pin low for SMBus slave mode. See Table 4.
SDA
I/O, 3.3-V Data Input and Open Drain Output
18
LVCMOS, External 2-kΩ to 5-kΩ pullup resistor is required.
Open Drain Pin is 3.3-V LVCMOS tolerant.
SDC
I/O, 3.3-V Clock Input and Open Drain Clock Output
17
LVCMOS, External 2-kΩ to 5-kΩ pullup resistor is required.
Open Drain Pin is 3.3-V LVCMOS tolerant.
ADDR_0
ADDR_1
ADDR_2
ADDR_3
45
40
21
16
I, 2.5-V
LVCMOS
Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer.
These pins are strap inputs. Their state is read on power-up to set the SMBus address in
SMBus control mode.
High = 1 kΩ to VDD, Low = 1 kΩ to GND
These pins are shared with the lock indicator functions. See Table 1.
POWER
3, 6, 7,
V_DD
10, 15,
Power
V_DD = 2.5 V ± 5%
46
GND
22, 27,
30, 31,
34, 39
Power
Ground reference.
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board with at least 4 vias to lower the ground impedance and improve
the thermal performance of the package.
4
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