DS125RT410_15 Datasheet, PDF (32/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
Register 0x15, Bit 2,
dvr_dem[2]
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 12. Driver De-Emphasis Settings
Register 0x15, Bit 1,
drv_dem[1]
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Register 15, Bit 0,
drv_dem[0]
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Register 0x15, Bit 6,
drv_dem_range
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
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De-emphasis Setting
(dB)
0.0
–1.5
–2.0
–3.5
–4.2
–5.0
–6.0
–6.5
–7.2
–8.0
–9.0
–9.5
–11.0
–13.0
–15.0
7.6 Register Maps
7.6.1 Register Information
There are two types of device registers in the DS125RT410. These are the control/shared registers and the
channel registers. The control/shared registers control or allow observation of settings which affect the operation
of all channels of the DS125RT410. They are also used to select which channel of the device is to be the target
channel for reads from and writes to the channel registers.
The channel registers are used to set all the configuration settings of the DS125RT410. They provide
independent control for each channel of the DS125RT410 for all the settable device characteristics.
Any registers not described in the tables that follow should be treated as reserved. The user should not try to
write new values to these registers. The user-accessible registers described in the tables that follow provide a
complete capability for customizing the operation of the DS125RT410 on a channel-by-channel basis.
7.6.2 Bit Fields in the Register Set
Many of the registers in the DS125RT410 are divided into bit fields. This allows a single register to serve multiple
purposes, which may be unrelated.
Often configuring the DS125RT410 requires writing a bit field that makes up only part of a register value while
leaving the remainder of the register value unchanged. The procedure for accomplishing this is to read in the
current value of the register to be written, modify only the desired bits in this value, and write the modified value
back to the register. Of course, if the entire register is to be changed, rather than just a bit field within the
register, it is not necessary to read in the current value of the register first.
In all the register configuration procedures described in the following sections, this procedure should be kept in
mind. In some cases, the entire register is to be modified. When only a part of the register is to be changed,
however, the procedure described previously should be used.
7.6.3 Writing to and Reading from the Control/Shared Registers
Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the
DS125RT410 with an address of 0xff.
Bit 2 of register 0xff is used to select either the control/shared register set or a channel register set. If bit 2 of
register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are
directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1).
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