DS125RT410_15 Datasheet, PDF (33/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
Register Maps (continued)
There is a register with address 0x00 in the control/shared register set, and there is also a register with address
0x00 in each channel register set. If you read the value in register 0x00 when bit 2 of register 0xff is cleared to 0,
then the value returned by the DS125RT410 is the value in register 0x00 of the control/shared register set. If you
read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS125RT410
is the value in register 0x00 of the selected channel register set. The channel register set is selected by bits 1:0
of register 0xff.
If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register
address will write all the channel register sets in the DS125RT410 simultaneously. This situation will persist until
either bit 3 of register 0xff or bit 2 of register 0xff is cleared. Note that when you write to register 0xff,
independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared
register 0xff. This channel select register, register 0xff, is unique in this regard.
Table 13 lists the control/shared register set. Any register addresses or register bits in the control/shared register
set not listed in this table should be considered reserved. In this table, the mode is either R for Read-Only, R/W
for Read-Write, or R/W/SC for Read-Write-Self-Clearing. If you try to write to a Read-Only register, the
DS125RT410 will ignore it.
ADDRESS
(HEX)
BITS
0
7
6
5
4
3:0
1
7
6
5
4
3
2
1
0
2
7:0
3
7:0
4
7
6
5
4
3
2
1
0
5
7
6:5
4
3
2
1
0
6
7:0
7
7:0
DEFAULT
VALUE
(HEX)
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0x05
Table 13. Control/Shared Registers
MODE EEPROM FIELD NAME
DESCRIPTION
R
N
SMBus_Addr3
SMBus Address
R
N
SMBus_Addr2
Strapped 7-bit address is 0x18 + SMBus_Addr[3:0]
R
N
SMBus_Addr1
R
N
SMBus_Addr0
RESERVED
R
N
Version2
Device version
R
N
Version1
R
N
Version0
R
N
Device_ID4
Device ID code
R
N
Device_ID3
R
N
Device_ID2
R
N
Device_ID1
R
N
Device_ID0
RW
N
RESERVED
N
RESERVED
RW
N
RESERVED
RWSC
N
RST_SMB_REGS
1: Resets share registers. Self-clearing.
RWSC
N
RST_SMB_MAS
1: Reset for SMBus Master Mode
RW
N
rc_eeprm_rd
1: Force EEPROM Configuration
RW
N
RESERVED
RW
N
RESERVED
RW
N
RESERVED
RW
N
RESERVED
RW
N
disab_eeprm_cfg
Disable Master Mode EEPROM Configuration
RW
N
RESERVED
R
N
EEPROM_READ_DON This bit is set to 1 when read from EEPROM is done
E
R
N
int_ch0
Set on Channel 0 Interrupt
R
N
int_ch1
Set on Channel 1 Interrupt
R
N
int_ch2
Set on Channel 2 Interrupt
R
N
int_ch3
Set on Channel 3 Interrupt
RW
N
RESERVED
RW
N
RESERVED
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