DS125RT410_15 Datasheet, PDF (16/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
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We write the lower-order byte, 0x80 into registers 0x60 and 0x62. We write the higher order byte, 0x2a, into the
least-significant 7 bits of registers 0x61 and 0x63. We also set bit 7 of registers 0x61 and 0x63. When this
operation is complete, registers 0x60 and 0x62 will contain a value of 0x80. Registers 0x61 and 0x63 will contain
a value of 0xaa.
We also write the PPM tolerance into both the upper and lower four bits of register 0x64. If we write this register
to a value of 0xff, then the PPM count tolerance in parts per million will be given by Equation 6.
Tol_PPM = (1 × 10^-6 × N_TOL) / N_PPM = 1379 parts per million
(6)
This value will be appropriate for most systems.
In summary, for data rates that correspond to the pre-defined standards for the DS125RT410, the standards-
based mode of operation can be used. This mode offers automatic switching of the divide ratio (and, for 10 GbE
and 1 GbE, the VCO frequency) to easily accommodate operation over harmonically-related data rates. For data
rates that are not covered by the pre-defined standards, the frequency-range-based mode of operation can be
used. This mode works with a fixed divider ratio, which is nominally 1. However, the divider ratio can be forced to
other values if desired.
The register configuration procedure is as follows:
1. Select the desired channel of the DS125RT410 by writing the appropriate value to register 0xff.
2. Set bits 5:4 of register 0x36 to a value of 2'b11 as described previously to enable the 25-MHz reference
clock.
3. Write registers 0x2f with the correct values.
4. Compute the expected PPM count values for Group 0 and Group 1 as described previously.
5. Write the expected PPM count values into registers 0x60-0x63 as described previously, setting bit 7 of both
registers 0x61 and 0x63.
6. Set the value 0xff into register 0x64 for an approximate PPM count tolerance of 1100-1400 PPM.
7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a.
If there is a signal at the correct data rate present at the input to the DS125RT410, the retimer will lock to it.
In ref_mode 3, bits 5:4 of register 0x36 are set to 2'b11, it is not necessary to set the CAP DAC values the
DS125RT410 determines the correct CAP DAC values automatically.
Because it is not necessary to set the CAP DAC values for Group 0 and Group 1 a-priori in ref_mode 3, the
DS125RT410 can be set up to use automatically switching divider ratios and arbitrary VCO frequencies in this
mode. The mapping of values in register 0x2f, bits 7:4, versus the divider ratios used for each of the two groups
is listed in Table 3.
Table 3. Divider Ratio Settings versus Register 0x2f Setting
REGISTER
0x2f, Bits 7:4
4'b0010
4'b0011
4'b0100
4'b0110
4'b1010
4'b1011
4'b1100
4'b1111
DIVIDER
RATIO
GROUP 0
1, 2, 4
1, 2, 4
2, 4
1, 2, 4, 8
2
2, 4
1
8
DIVIDER
RATIO
GROUP 1
1, 2, 4
1, 2, 4
2, 4
1, 2, 4, 8
2
2, 4
1
1
16
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