DS125RT410_15 Datasheet, PDF (7/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges with default register settings unless otherwise specified⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
DRIVER OUTPUTS (TXPn, TXNn)
V_OD0
Differential output voltage
Differential measurement with OUT+ and OUT–
terminated by 50 Ω to GND, AC-Coupled,
SMBus register VOD control (Register 0x2d bits 2:0) set
400
to 0, minimum VOD
De-emphasis control set to minimum (0 dB)
675 mV_P-P
V_OD7
Differential output voltage
Differential measurement with OUT+ and OUT-
terminated by 50 Ω to GND, AC-Coupled
SMBus register VOD control (Register 0x2d bits 2:0) set
to 7, maximum VOD
De-emphasis control set to minimum (0 dB)
1000
mV_P-P
V_{OD_DE}
De-emphasis level⁽⁹⁾
Differential measurement with OUT+ and OUT-
terminated by 50 Ω to GND, AC-Coupled
Set by SMBus register control to maximum de-
emphasis setting
Relative to the nominal 0 dB de-emphasis level set at
the minimum de-emphasis setting
–15
dB
t_R, t_F
Transition time (rise and fall times)^{(9) (10)}
Transition time control = Full slew rate
Transition time control = Limited slew rate
39
ps
50
ps
L_RO
Maximum differential output return loss -
|SDD22|
100 MHz to 6 GHz⁽¹¹⁾
–15
dB
t_DP
Propagation delay
T_DE
De-emphasis pulse duration⁽¹²⁾
Retimed data
Measured at V_OD = 1000 mV_P-P,
de-emphasis setting = –12 dB
300
ps
75
ps
TJ
Output total jitter
Measured at BER = 10^–12(13)
10
ps
T_SKEW
Intra pair skew
Channel-to-channel skew
Difference in 50% crossing between TXPn and TXNn
for any output
3
ps
7
ps
CLOCK AND DATA RECOVERY
BW_PLL
J_TOL
PLL bandwidth, –3 dB
Input sinusoidal jitter tolerance
10-kHz to 250-MHz sinusoidal jitter
frequency
Measured at 10.3125 Gbps
Measured at BER = 10^-15
5
MHz
0.6
UI
J_TRANS
Jitter transfer sinusoidal jitter at 10 MHz
jitter frequency
Measured at BER = 10^-15
–6
dB
Fixed (manual setting) of CTLE, HEO/VEO lock monitor
disabled (register 0x3e, bit 7 set to 0)
2
ms
T_LOCK
CDR lock time, Ref_mode 3,
Fixed data rate (for example, 10.3125
Gbps)
Fixed (manual setting) of CTLE, HEO/VEO lock monitor
enabled (register 0x3e, bit 7 set to 1 - default)
12
ms
Medium (20 inch) channel loss with CTLE adaption,
HEO/VEO lock monitor must be enabled ⁽¹⁴⁾
74
ms
RECOMMENDED REFERENCE CLOCK SPECIFICATIONS
REF_f
REFCLK
_IN_PW
REFCLK
_OUT_DCD
REF_VIH
REF_VIL
Input reference clock frequency
Minimum REFCLK_IN pulse width
At REFCLK_IN pin
REFCLK_OUT duty cycle distortion
Reference clock input min high threshold
Reference clock input max low threshold
C_L = 5 pF
24.9975
25 25.0025
4
MHz
ns
0.55
ns
1.75
V
0.7
V
(9) Measured with clock-like {11111 00000} pattern.
(10) Slew rate is controlled by SMBus register settings.
(11) Measured with 10-MHz clock pattern output.
(12) De-emphasis pulse width varies with V_OD and de-emphasis settings.
(13) Typical with no output de-emphasis, minimum output transmission channel.
(14) The CDR lock time is when the input has a valid signal to when the output sends retimed data. The CDR lock time is after the CTLE
adaption is completed.
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