DS125RT410_15 Datasheet, PDF (35/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
Table 15. Channel Registers
ADDRESS
(HEX)
0
BITS
7:4
3
DEFAULT
VALUE
(Hex)
0
0
MODE
RW
RW
EEPROM
FIELD NAME
N
RESERVED
N
RST_CORE
2
0
RW
N
RST_REGS
1
0
RW
N
RST_REFCLK
0
0
RW
N
RST_VCO
1
7:5
0
RW
N
RESERVED
4
0
R
N
CDR_LOCK_LOSS_INT
3:1
0
R
N
RESERVED
0
0
R
N
SIG_DET_LOSS_INT
2
7:0
0x0
R
N
cdr_status
3
7
0
RW
Y
EQ_BST0[1]
6
0
RW
Y
EQ_BST0[0]
5
0
RW
Y
EQ_BST1[1]
4
0
RW
Y
EQ_BST1[0]
3
0
RW
Y
EQ_BST2[1]
2
0
RW
Y
EQ_BST2[0]
1
0
RW
Y
EQ_BST3[1]
0
0
RW
Y
EQ_BST3[0]
4
7:0
0
RW
N
RESERVED
5
7:0
0
RW
N
RESERVED
6
7:0
0
RW
N
RESERVED
7
7:0
0
RW
N
RESERVED
DESCRIPTION
1: Reset core state machine
0: Normal Operation
1: Resets channel registers, restores default values
0: Normal Operation
1: Reset reference clock domain
0: Normal Operation
1: Reset VCO DIV clock domain
0: Normal Operation
1: indicates loss of CDR lock after having acquired it.
Bit clears on read.
Loss of signal indicator.
Bit is set once signal is acquired and then lost.
CDR Status [7:0]
Bit[7] = PPM Count met
• 1: The data rate is within the specified PPM tolerance (typically
around ±1000 ppm unless specified otherwise in Reg 0x64).
• 0: Error: PPM tolerance exceeded.
Bit[6] = Auto Adapt Complete
• 1: CTLE auto-adaption is complete.
• 0: CTLE auto-adaption in progress.
Bit[5] = Fail Lock Check
• 1: Signal quality and amplitude level is not sufficient for lock.
• 0: Signal quality and amplitude level is sufficient for CDR lock.
Bit[4] = Lock
• When asserted, indicates CDR is locked to the incoming signal.
Bit[3] = CDR Lock
• When asserted, indicates CDR is locked to the incoming signal
(same status as bit 4).
Bit[2] = Single Bit Limit Reached
• 1: Number of bit transitions to acquire CDR lock has been met.
• 0: Not enough bit transitions within the CDR lock time window to
declare lock.
Bit[1] = Comp LPF High
• 1: Data rate exceeds the VCO upper limit, based on loop filter
comparator voltage.
• 0 = Data rate is within VCO upper limit.
Bit[0] = Comp LPF Low
• 1: Data rate is below the VCO lower limit, based on loop filter
comparator voltage.
• 0 = Data rate is within VCO lower limit.
This register can be used to force an EQ boost setting if used in
conjunction with channel register 0x2D[3].
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