DS125RT410_15 Datasheet, PDF (29/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

www.ti.com
DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
7.5.18 Setting the Adaptation/Lock Mode
Register 0x31, bits 6:5, and Register 0x33, bits 7:4 and 3:0, Register 0x34, bits 3:0, Register 0x35, bits 4:0,
Register 0x3e, bit 7, and Register 0x6a
There are two adaptation modes available in the DS125RT410.
• Mode 0: The user is responsible for setting the CTLE. This mode is used if the transmission channel
response is fixed.
• Mode 1: The CTLE is adapted to equalize the transmission channel. This mode is primarily used for
smoothly-varying high-loss transmission channels such as cables and simple PCB traces.
Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the
adaptation algorithm is listed in Table 9.
REGISTER 0x31,
Bit 6
adapt_mode[1]
0
0
Table 9. DS125RT410 Adaptation Algorithm Settings
REGISTER 0x31,
Bit 5
adapt_mode[0]
0
1
ADAPT MODE SETTING <1:0>
ADAPTATION ALGORITHM
00
No Adaptation
01
Adapt CTLE Until Optimum (Default)
By default the DS125RT410 requires that the equalized internal eye exhibit horizontal and vertical eye openings
greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register
0x6a.
The DS125RT410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye
opening falls below the threshold set in register 0x6a, the DS125RT410 will declare a loss of lock.
The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of
register 0x3e.
7.5.19 Initiating Adaptation
Register 0x24, bit 2, and Register 0x2f, bit 0
When the DS125RT410 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is
selected using bits 6:5 in register 0x31, the DS125RT410 will also try to adapt its CTLE.
Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing
register 0x2f, bit 0.
7.5.20 Setting the Reference Enable Mode
Register 0x36, bits 5:4
The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a
value of 3 or 2'b11.
A 25-MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference
clock in the DS125RT410 is explained in the following.
First, the reference clock allows the DS125RT410 to calibrate its VCO frequency at power-up and upon reset.
This enables the DS125RT410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase
lock much faster. The DS125RT410 is not required to tune through the available coarse VCO tuning settings as it
tries to acquire lock to an input signal. It can select the correct setting immediately.
Second, if the DS125RT410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the
DS125RT410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly
allows the DS125RT410 to raise an interrupt indicating that it has lost lock quickly, which the system controller
can then service to correct the problem quickly.
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: DS125RT410
Submit Documentation Feedback
29