DS125RT410_15 Datasheet, PDF (43/58 Pages) Texas Instruments – Low-Power Multi-Rate Quad Channel Retimer

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DS125RT410
SNLS459A – APRIL 2013 – REVISED OCTOBER 2015
Table 15. Channel Registers (continued)
ADDRESS
(HEX)
36
BITS
7
6
5
4
DEFAULT
VALUE
(Hex)
0
0
1
1
MODE
RW
RW
RW
RW
EEPROM
FIELD NAME
Y
RESERVED
Y
HEO_VEO_INT_EN
Y
REF_MODE1
Y
REF_MODE0
3
0
RW
Y
RESERVED
2
0
RW
Y
CDR_CAP_DAC_RNG_OV
1
0
RW
Y
cdr_cap_dac_rng[1]
0
1
RW
Y
cdr_cap_dac_rng[0]
37
7
6
5
4
3
2
1
0
38
7
6
5
4
3
2
1
0
39
7
6
5
0
R
N
CTLE_STATUS7
0
R
N
CTLE_STATUS6
0
R
N
CTLE_STATUS5
0
R
N
CTLE_STATUS4
0
R
N
CTLE_STATUS3
0
R
N
CTLE_STATUS2
0
R
N
CTLE_STATUS1
0
R
N
CTLE_STATUS0
0
R
N
RESERVED
0
R
N
RESERVED
0
R
N
RESERVED
0
R
N
RESERVED
0
R
N
RESERVED
0
R
N
RESERVED
0
R
N
RESERVED
0
R
N
RESERVED
0
RW
N
RESERVED
0
RW
Y
EOM_RATE1
0
RW
Y
EOM_RATE0
4
3
2
1
0
3A
7
6
5
4
3
2
1
0
0
RW
Y
START_INDEX4
0
RW
Y
START_INDEX3
0
RW
Y
START_INDEX2
0
RW
Y
START_INDEX1
0
RW
Y
START_INDEX0
1
RW
Y
FIXED_EQ_BST0[1]
0
RW
Y
FIXED_EQ_BST0[0]
1
RW
Y
FIXED_EQ_BST1[1]
0
RW
Y
FIXED_EQ_BST1[0]
0
RW
Y
FIXED_EQ_BST2[1]
1
RW
Y
FIXED_EQ_BST2[0]
0
RW
Y
FIXED_EQ_BST3[1]
1
RW
FIXED_EQ_BST3[0]
DESCRIPTION
1: Enable HEO/VEO interrupt capability
11: Fast_lock all cap dac ref clock enabled (recommended)
10: constrained cap dac, ref clock enabled
01: referenceless constained cap dac
00: referenceless all cap dac
Over-ride enable for Cap DAC range
Sets the stop value based on start value - (rng+1):
11:stop = start - 4
10: stop = start - 3
01: stop = start - 2
00: stop = start - 1
Feature is reserved for future use
With eom_ov=1, these bits control the Eye Monitor Rate:
11: Use for Full Rate, Fastest
10 : Use for 1/2 Rate
01: Use for 1/4 Rate
00: Use for 1/8 Rate, Slowest
Start index for EQ adaptation
During adaptation, if the divider setting is >2, then a fixed EQ setting
from this register will be used. However, if channel register 0x6F[7] is
enabled, then an EQ adaptation will be performed instead
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