LM3S3749 Datasheet, PDF (812/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Signal Tables
Table 21-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PF2
I/O
TTL
GPIO port F bit 2.
60
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PF1
I/O
TTL
GPIO port F bit 1.
61
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
62
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
63
GND
-
Power Ground reference for logic and I/O pins.
64
RST
I
TTL
System reset input.
PB3
I/O
TTL
GPIO port B bit 3.
65
I2C0SDA
I/O
OD
I²C module 0 data.
PB0
I/O
TTL
GPIO port B bit 0.
66
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
PB1
I/O
TTL
GPIO port B bit 1.
67
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
68
VDD
-
Power Positive supply for I/O and some logic.
69
GND
-
Power Ground reference for logic and I/O pins.
70
USB0DM
I/O
Analog Bidirectional differential data pin (D- per USB specification) for
USB0.
71
USB0DP
I/O
Analog Bidirectional differential data pin (D+ per USB specification) for
USB0.
PB2
I/O
TTL
GPIO port B bit 2.
72
I2C0SCL
I/O
OD
I²C module 0 clock.
73
USB0RBIAS
O
Analog 9.1-kΩ resistor (1% precision) used internally for USB analog
circuitry.
PE0
I/O
TTL
GPIO port E bit 0.
74
SSI1Clk
I/O
TTL
SSI module 1 clock.
PE1
I/O
TTL
GPIO port E bit 1.
75
SSI1Fss
I/O
TTL
SSI module 1 frame.
PH4
I/O
TTL
GPIO port H bit 4.
76
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PC3
I/O
TTL
GPIO port C bit 3.
77
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
PC2
I/O
TTL
GPIO port C bit 2.
78
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
79
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
812
November 17, 2011
Texas Instruments-Production Data