LM3S3749 Datasheet, PDF (688/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
0
Name
TXRDY
Type
R/W
Reset
0
Description
Transmit Packet Ready
Value Description
0 No transmit packet is ready.
1 Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
Device Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
reserved CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY
Type RO
Reset
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit/Field
7
6
5
4
Name
reserved
CLRDT
STALLED
STALL
Type
RO
R/W
R/W
R/W
Reset
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
Endpoint Stalled
Value Description
0 A STALL handshake has not been transmitted.
1 A STALL handshake has been transmitted. The FIFO is flushed
and the TXRDY bit is cleared.
Software must clear this bit.
Send STALL
Value Description
0 No effect.
1 Issues a STALL handshake to an IN token.
Software clears this bit to terminate the STALL condition.
Note: This bit has no effect in isochronous transfers.
688
November 17, 2011
Texas Instruments-Production Data