LM3S3749 Datasheet, PDF (118/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Cortex-M3 Peripherals
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Note: This register can only be accessed from privileged mode.
The PEND0 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 87 for interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
INT
Type
Reset Description
R/W 0x0000.0000 Interrupt Set Pending
Value
0
1
Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
118
November 17, 2011
Texas Instruments-Production Data