LM3S3749 Datasheet, PDF (256/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Hibernation Module
6.4.4
6.4.5
6.5
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
Register Map
Table 6-2 on page 256 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled
before the registers can be programmed (see page 224). There must be a delay of 3 system clocks
after the Hibernation module clock is enabled before any Hibernation module registers are accessed.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and and have special timing requirements. Software
should make use of the WRC bit in the HIBCTL register to ensure that the required timing
gap has elapsed. See “Register Access Timing” on page 251.
Important: The Hibernation module registers are reset under two conditions:
1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are
both cleared.
2. A cold POR, when both the V_DD and V_BAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
Table 6-2. Hibernation Module Register Map
Offset Name
Type
Reset
Description
0x000 HIBRTCC
0x004 HIBRTCM0
0x008 HIBRTCM1
0x00C HIBRTCLD
RO
0x0000.0000 Hibernation RTC Counter
R/W
0xFFFF.FFFF Hibernation RTC Match 0
R/W
0xFFFF.FFFF Hibernation RTC Match 1
R/W
0xFFFF.FFFF Hibernation RTC Load
See
page
258
259
260
261
256
November 17, 2011
Texas Instruments-Production Data