LM3S3749 Datasheet, PDF (199/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Stellaris® LM3S3749 Microcontroller
Bit/Field
21
20
19:17
16:14
13
12
11
Name
reserved
USEPWMDIV
PWMDIV
reserved
PWRDN
reserved
BYPASS
Type
RO
R/W
R/W
RO
R/W
RO
R/W
Reset
0
0
0x7
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-4 on page 183 for programming guidelines.
Note:
The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
November 17, 2011
199
Texas Instruments-Production Data