LM3S3749 Datasheet, PDF (55/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Stellaris® LM3S3749 Microcontroller
1.4.5.3
1.4.6
1.4.6.1
1.4.6.2
1.4.6.3
1.4.7
1.4.7.1
Watchdog Timer (see page 447)
A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
Memory Peripherals
The LM3S3749 controller offers both single-cycle SRAM and single-cycle Flash memory.
SRAM (see page 271)
The LM3S3749 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Flash (see page 272)
The LM3S3749 Flash controller supports 128 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
ROM (see page 846)
The LM3S3749 microcontroller ships with the Stellaris family Peripheral Driver Library conveniently
preprogrammed in read-only memory (ROM). The Stellaris Peripheral Driver Library is a royalty-free
software library for controlling on-chip peripherals, and includes a boot-loader capability. The library
performs both peripheral initialization and peripheral control functions, with a choice of polled or
interrupt-driven peripheral support, and takes full advantage of the stellar interrupt performance of
the ARM® Cortex™-M3 core. No special pragmas or custom assembly code prologue/epilogue
functions are required. For applications that require in-field programmability, the royalty-free Stellaris
boot loader included in the Stellaris Peripheral Driver Library can act as an application loader and
support in-field firmware updates.
Additional Features
JTAG TAP Controller (see page 163)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
November 17, 2011
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