LM3S3749 Datasheet, PDF (12/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Table of Contents
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 555
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 556
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 556
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 557
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 558
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 558
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 559
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 560
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 560
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 561
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 562
Figure 15-1. I²C Block Diagram ............................................................................................. 592
Figure 15-2. I²C Bus Configuration ........................................................................................ 593
Figure 15-3. START and STOP Conditions ............................................................................. 593
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 594
Figure 15-5. R/S Bit in First Byte ............................................................................................ 594
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 594
Figure 15-7. Master Single SEND .......................................................................................... 598
Figure 15-8. Master Single RECEIVE ..................................................................................... 599
Figure 15-9. Master Burst SEND ........................................................................................... 600
Figure 15-10. Master Burst RECEIVE ...................................................................................... 601
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 602
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 603
Figure 15-13. Slave Command Sequence ................................................................................ 604
Figure 16-1. USB Module Block Diagram ............................................................................... 629
Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 723
Figure 17-2. Structure of Comparator Unit .............................................................................. 724
Figure 17-3. Comparator Internal Reference Structure ............................................................ 725
Figure 18-1. PWM Unit Diagram ............................................................................................ 736
Figure 18-2. PWM Module Block Diagram .............................................................................. 737
Figure 18-3. PWM Count-Down Mode .................................................................................... 738
Figure 18-4. PWM Count-Up/Down Mode .............................................................................. 739
Figure 18-5. PWM Generation Example In Count-Up/Down Mode ........................................... 739
Figure 18-6. PWM Dead-Band Generator ............................................................................... 740
Figure 19-1. QEI Block Diagram ............................................................................................ 791
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 792
Figure 20-1. 100-Pin LQFP Package Pin Diagram .................................................................. 808
Figure 23-1. Load Conditions ................................................................................................ 830
Figure 23-2. JTAG Test Clock Input Timing ............................................................................. 833
Figure 23-3. JTAG Test Access Port (TAP) Timing .................................................................. 833
Figure 23-4. External Reset Timing (RST) .............................................................................. 834
Figure 23-5. Power-On Reset Timing ..................................................................................... 834
Figure 23-6. Brown-Out Reset Timing .................................................................................... 834
Figure 23-7. Software Reset Timing ....................................................................................... 834
Figure 23-8. Watchdog Reset Timing ..................................................................................... 835
Figure 23-9. Hibernation Module Timing ................................................................................. 836
Figure 23-10. ADC Input Equivalency Diagram ......................................................................... 837
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November 17, 2011
Texas Instruments-Production Data