LM3S3749 Datasheet, PDF (14/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Revision History .................................................................................................. 29
Documentation Conventions ................................................................................ 36
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 62
Processor Register Map ....................................................................................... 63
PSR Register Combinations ................................................................................. 68
Memory Map ....................................................................................................... 76
Memory Access Behavior ..................................................................................... 79
SRAM Memory Bit-Banding Regions .................................................................... 81
Peripheral Memory Bit-Banding Regions ............................................................... 81
Exception Types .................................................................................................. 87
Interrupts ............................................................................................................ 87
Exception Return Behavior ................................................................................... 92
Faults ................................................................................................................. 93
Fault Status and Fault Address Registers .............................................................. 94
Cortex-M3 Instruction Summary ........................................................................... 96
Core Peripheral Register Regions ......................................................................... 99
Memory Attributes Summary .............................................................................. 102
TEX, S, C, and B Bit Field Encoding ................................................................... 105
Cache Policy for Memory Attribute Encoding ....................................................... 106
AP Bit Field Encoding ........................................................................................ 106
Memory Region Attributes for Stellaris Microcontrollers ........................................ 106
Peripherals Register Map ................................................................................... 107
Interrupt Priority Levels ...................................................................................... 132
Example SIZE Field Values ................................................................................ 160
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 164
JTAG Port Pins Reset State ............................................................................... 165
JTAG Instruction Register Commands ................................................................. 171
System Control & Clocks Signals (100LQFP) ...................................................... 175
Reset Sources ................................................................................................... 176
Clock Source Options ........................................................................................ 181
Possible System Clock Frequencies Using the SYSDIV Field ............................... 183
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 183
System Control Register Map ............................................................................. 187
RCC2 Fields that Override RCC fields ................................................................. 205
Hibernate Signals (100LQFP) ............................................................................. 250
Hibernation Module Register Map ....................................................................... 256
Flash Protection Policy Combinations ................................................................. 273
User-Programmable Flash Memory Resident Registers ....................................... 275
Flash Register Map ............................................................................................ 275
DMA Channel Assignments ............................................................................... 302
Request Type Support ....................................................................................... 303
Control Structure Memory Map ........................................................................... 304
Channel Control Structure .................................................................................. 304
μDMA Read Example: 8-Bit Peripheral ................................................................ 313
μDMA Interrupt Assignments .............................................................................. 314
Channel Control Structure Offsets for Channel 30 ................................................ 315
14
November 17, 2011
Texas Instruments-Production Data