LM3S3749 Datasheet, PDF (185/898 Pages) Texas Instruments – Stellaris® LM3S3749 Microcontroller

Stellaris® LM3S3749 Microcontroller
5.2.5.7
5.2.5.8
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 198 and page 205).
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T_READY (see Table
23-9 on page 830). During the relock time, the affected PLL is not usable as a clock reference.
Either PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the T_READY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When the XTAL value is
greater than 0x0f, the down counter is set to 0x2400 to maintain the required lock time on higher
frequency crystal inputs. Hardware is provided to keep the PLL from being used as a system clock
until the T_READY condition is met after one of the two changes above. It is the user's responsibility
to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched
to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (T_READY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
The USB PLL is not protected during the lock time (T_READY) and software should ensure that the
USB PLL has locked before using the interface. Software can use many methods to ensure the
T_READY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt
Status (RIS) register, and enabling the USB PLL Lock interrupt.
Main Oscillator Verification Circuit
A circuit is added to ensure that the main oscillator is running at the appropriate frequency. The
circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable
band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. If the internal oscillator (IOSC) is disabled, it is enabled.
3. The system clock is switched from the main oscillator to the IOSC.
4. An internal power-on reset is initiated that lasts for 32 IOSC periods.
5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
November 17, 2011
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